In the semiconductor industry, there is a constant demand to increase the operating speed of integrated circuits (ICs). This increased demand is fueled by the need for electronic devices such as computers to operate at increasingly greater speeds. The demand for increased speed, in turn, has resulted in a continual size reduction of the semiconductor devices. Specifically, the channel length, junction depths, and/or gate dielectric thickness of field effect transistors (FETs) are reduced. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical FET to increase the overall speed of the FET. Additionally, reducing the size, or scale, of the components of a typical FET also increases the density and number of FETS that can be fabricated on a given single semiconductor wafer.
However, reducing the channel length of a transistor also increases “short-channel” effects, as well as “edge effects” that are relatively unimportant in long channel transistors. Short-channel effects include, among other things, an increased source/drain (S/D) leakage current when the transistor is switched “off”. One of the edge effects that may influence transistor and circuit performance is known as the total gate-to-drain and gate-to-source capacitance. Gate-drain capacitance is also known as “Miller capacitance” due to a Miller multiplication factor, which increases the capacitance by a factor related to the voltage gain of a transistor. The Miller multiplication further increases the parasitic gate-to-drain capacitance that slows down circuits. As is known to those skilled in the art, a significant portion of gate-to-drain and gate-to-source or Miller capacitance is an overlap capacitance that arises between the gate conductor and the S/D metal contact.
Coupled with the Miller effect, this overlap capacitance contributes significantly to the overall switching capacitance, which in turn reduces the operation speed of the device.
Therefore, there is a continuing need for reducing the gate-to-source/drain metal contact capacitance in FET devices.